In accordance with the Moore's Law, the number of transistors on an integrated circuit doubles every two years. Although such a high packing density allows more functions to be incorporated per unit area of an integrated circuit, it is becoming increasingly difficult for foundries to manufacture a defect free integrated circuit as packing densities continue to increase. This predicament has exalted the significance of Design-for-Testability (DFT) in an integrated circuit design. Scan chain testing, for example, is one of various techniques that utilize DFT methods to detect manufacturing faults in an integrated circuit. One or more scan flip-flops are typically used to perform a scan chain testing on an integrated circuit.
Generally, conventional scan flip-flops use one or more clock inversion or buffer circuits, e.g., a transmission gate, to generate a complementary clock signal to perform a scan chain test. However, the transmission gate in a scan flip-flop typically occupies a relatively large area of an integrated circuit, which may disadvantageously require allocation of valuable real estate of the integrated circuit (IC), and, in turn, increase design complexity of the IC. Moreover, operating such transmission gates typically consumes additional power. Thus, conventional scan flip-flops have not been entirely satisfactory.